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Abstract

A testing method and device for detecting the existence of 'stuck-open', faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.

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First Claim