High performance multi-bank compact synchronous DRAM architecture
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United States of America Patent
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Aug 27, 2002
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N/A
app pub date -
Feb 6, 2001
filing date -
Feb 8, 2000
priority date (Note) -
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Abstract
Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the virtual memory banks has coupled to it an associated segmented sense amp which responds to an appropriate bank select signal by sensing data stored in a selected memory bank segment. The segmented sense amp uses a segmented bit line to reduce bit sense latency without decreasing bit density or increasing chip size.
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