Digital isolation system with hybrid circuit in ADC calibration loop

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United States of America Patent

PATENT NO 6442213
SERIAL NO

09035180

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Abstract

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An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

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Patent Owner(s)

Patent OwnerAddress
SILICON LABORATORIES INC400 W CESAR CHAVEZ AUSTIN TX 78701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dupuis, Timothy J Austin, TX 97 1650
Krone, Andrew W Austin, TX 35 884
Scott, Jeffrey W Austin, TX 162 3356
Sooch, Navdeep S Austin, TX 85 1879
Welland, David R Austin, TX 151 3701

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