Reduced transistors data switch port wherein each of a plurality of transmission gates is coupled to both first and second control signals for selectively enabling
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 27, 2002
Grant Date -
N/A
app pub date -
Mar 23, 1999
filing date -
Mar 23, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully