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Abstract

A communication system for transferring (Peripheral Component Interconnect) PCI and non-PCI data over a non-PCI bus is disclosed. The system bus is a non-PCI bus having an address bus and a data bus for communicating addresses and data. A PCI-compatible peripheral is coupled to the non-PCI bus for transmitting and receiving PCI-compatible data. A non-PCI device is also coupled to the non-PCI bus for transmitting and receiving non-PCI data. In addition, a slave device is also coupled to the non-PCI bus for receiving and transmitting non-PCI data and PCI data. A byte size control line capable of being driven by the PCI-compatible peripheral and the non-PCI device is coupled between the PCI-compatible peripheral, the non-PCI device, and the slave device for indicating whether data appearing on the data bus is from the PCI-compatible peripheral or the non-PCI device, and for indicating how many bytes on the data bus are actually valid, if the data appearing on the non-PCI bus is from the non-PCI device. A bus byte enable (BBE) driven by the PCI-compatible peripheral is also coupled between the PCI-compatible peripheral and the slave device for indicating which bytes on the data bus are valid. The slave device decodes the byte size control line, the BBE, and the address bus to accept valid bytes of PCI-compatible data and non-PCI data appearing on the data bus.

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First Claim