Method and apparatus for interfacing memory with a bus
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United States of America Patent
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Aug 27, 2002
Grant Date -
N/A
app pub date -
Aug 18, 1999
filing date -
Aug 18, 1999
priority date (Note) -
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Abstract
A method and apparatus for interfacing memory with a bus in a computer system includes processing that begins by receiving a transaction from the bus. The transaction may be a read transaction and/or a write transaction. Upon receiving the transaction, the process continues by validating the received transaction and, when valid, acknowledges its receipt. The processing then continues by storing the physical address, which was included in the received transaction, and the corresponding command in an address/control buffer. The processing continues by retrieving the physical address from the address/control buffer when the transaction is to be processed. The determination of when the transaction is to be processed is based on an ordering within the address/control buffer. The processing then continues by performing the transaction utilizing a first or second memory path based on the physical address, such that a first or second memory is accessed.
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