US Patent No: 6,445,643

Number of patents in Portfolio can not be more than 2000

Method and apparatus for setting write latency

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ALSO PUBLISHED AS: 20010012234
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Importance

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Abstract

A method of setting write latency and a write/valid indicator circuit for use with the method. In a preferred embodiment, time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. The write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ROUND ROCK RESEARCH, LLCBOISE, ID3576

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Johnson, Brian Devon, GB 193 1787
Keeth, Brent Boise, ID 298 5687

Cited Art

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (2)
5,813,023 Method and apparatus for multiple latency synchronous dynamic random access memory 41 1997
5,910,920 High speed input buffer 42 1997
 
ADVANCED MEMORY INTERNATIONAL, INC. (1)
6,088,774 Read/write timing for maximum utilization of bidirectional read/write bus 81 1997
 
ANALOG DEVICES, INC. (1)
5,922,076 Clocking scheme for digital signal processor system 15 1997
 
ELPIDA MEMORY, INC. (1)
6,212,127 Semiconductor device and timing control circuit 24 2000
 
HITACHI, LTD. (1)
5,933,623 Synchronous data transfer system 23 1996
 
INTEL CORPORATION (1)
5,903,916 Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation 22 1996
 
MORGAN STANLEY & CO., INCORPORATED (1)
5,933,155 System and method for buffering multiple frames while controlling latency 34 1996
 
S. AQUA SEMICONDUCTOR, LLC (1)
5,890,195 Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram 33 1997
 
SLORAM, INC. (1)
5,917,760 De-skewing data signals in a memory system 182 1997
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,966,343 Variable latency memory circuit 22 1997

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (6)
7,058,799 Apparatus and method for clock domain crossing with integrated decode 5 2001
6,801,073 System, circuit and method for low voltage operable, small footprint delay 1 2002
7,336,547 Memory device having conditioning output data 1 2004
7,092,312 Pre-emphasis for strobe signals in memory device 8 2004
7,397,712 Pre-emphasis for strobe signals in memory device 2 2006
7,643,370 Memory device having conditioning output data 0 2006
 
ROUND ROCK RESEARCH, LLC (5)
6,697,926 Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device 146 2001
6,697,297 Apparatus for setting write latency 7 2002
7,289,378 Reconstruction of signal timing in integrated circuits 3 2004
7,489,569 Reconstruction of signal timing in integrated circuits 1 2006
7,453,746 Reconstruction of signal timing in integrated circuits 1 2007
 
HYNIX SEMICONDUCTOR INC. (1)
8,027,205 Semiconductor memory device and operation method thereof 1 2009
 
NANYA TECHNOLOGY CORPORATION (1)
7,940,543 Low power synchronous memory command address scheme 0 2008
 
SAMSUNG ELECTRONICS CO., LTD. (1)
7,296,110 Memory system and data channel initialization method for memory system 4 2005

Maintenance Fees

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11.5 Year Payment $7400.00 $3700.00 $1850.00 Mar 3, 2014
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