ATM switch with VC priority buffers
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United States of America Patent
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Sep 3, 2002
Grant Date -
N/A
app pub date -
Mar 5, 1998
filing date -
Oct 3, 1995
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The present ATM switch includes a plurality of controllers, each of which contains a plurality of cell buffers to store cells for each VC. A plurality of arbitration buffers store pointers, on a VC priority level basis, to order the processing of cell transmissions. The arbitration buffers are processed in priority order, with an interrupt being generated by a timer associated with each arbitration buffer, other than the highest priority arbitration buffer, to ensure that each arbitration buffer is periodically processed.
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