Virtual address bypassing using local page mask
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United States of America Patent
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-
Sep 3, 2002
Grant Date -
N/A
app pub date -
Feb 19, 2000
filing date -
Feb 19, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page sizing. The TLB includes a content addressable memory (CAM) containing the virtual page numbers corresponding to pages in the cache and a random access memory (RAM) storing the physical page numbers of the pages corresponding to the virtual page numbers in the CAM. The physical page number RAM stores a page mask along with the physical page numbers, and includes local multiplexers which perform virtual address bypassing of the physical page number when the page has been masked.
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