Adaptive manufacturing of semiconductor circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Sep 10, 2002
Grant Date -
N/A
app pub date -
Apr 7, 2000
filing date -
Apr 7, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention relates to a process for implementing a base circuit design with configurable modifications to compensate for variations in component parameters due to material or processing characteristics. During the fabrication process, the base circuit is electrically tested to determine the characteristics of the base circuit given the materials and processes used to implement the circuit. Based on the testing, subsequent processing steps are used to modify the base circuit as necessary to compensate for variations in the circuit or component parameters due to the material or processing characteristics. Preferably, the base circuit includes hetero-junction bipolar transistors and the in-process testing is used to determine an associated beta value for the transistor. Based upon the determined beta value, the circuit is modified during processing to insure proper quiescent currents occur during normal operation given the beta of the transistor. Preferably, a top level mask is used to select the resistance in the base current path to select the proper base current for a desired quiescent collector current.
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