Importance

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Abstract

The present invention utilizes a plurality of transistors configured such that the drain/well diode of the PMOS switch is not forward biased during any part of the charge pump cycle. In one embodiment a plurality of transistors are coupled between the drain, source and well of the PMOS switch such that the well of the PMOS switch is connected to a voltage that is one base-emitter voltage drop (Vbe) less than the higher of either the source voltage or the drain voltage. Since the well is always a single Vbe below the higher of the source voltage or the drain voltage, the gate-well diodes of the PMOS switches are prevented from becoming forward biased, thereby reducing current drain and resulting in improved efficiency of the charge pump. A further embodiment utilizes a plurality of switches and a specific switching sequence such that certain switches at a first side of the pump capacitors are allowed to float while certain switches at the second side of the pump capacitors are being configured, then once the switches at the second side of the pump capacitors are configured, the switches at the first side of the pump capacitors are used to transfer the charge from one capacitor to another. Accordingly, the drain-well diode of the PMOS switches are not forward biased during the charge pump cycles.

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First Claim