Circuits and methods for linearizing capacitor calibration and systems using the same
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United States of America Patent
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Sep 10, 2002
Grant Date -
N/A
app pub date -
Jul 30, 2001
filing date -
Jul 30, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A switched capacitor circuit includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array. A first plurality of switches selectively couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch samples the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node. A second plurality of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected onto the node.
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