Flash memory cell for high efficiency programming
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United States of America Patent
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Sep 10, 2002
Grant Date -
Jan 3, 2002
app pub date -
Aug 1, 2001
filing date -
Dec 17, 1999
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
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