Using non-volatile memory for power management in a computer
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United States of America Patent
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Sep 10, 2002
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app pub date -
Dec 14, 1999
filing date -
Dec 14, 1999
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Abstract
A computer system includes a processor and a non-volatile memory device coupled to the processor. The processor either generates or receives a command to enter a low-power mode. The non-volatile memory device includes a first area reserved for random-access read/write cycles by the processor and a second area reserved for storing processor state information upon entering the low-power mode. The processor and the memory device both are configured to lose power during the low-power mode. In some embodiments, the memory device also serves as a read-only memory device and as a persistent storage device for data and application programs.
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