High-speed data transfer synchronizing system and method
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United States of America Patent
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Sep 10, 2002
Grant Date -
N/A
app pub date -
May 7, 1999
filing date -
May 7, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
One memory controller and a plurality of memory modules are connected to a data bus line, clock bus line, and command bus line. Each memory module includes an internal clock signal generating circuit for generating internal clocks synchronizing with external clock signals output from the memory controller. This internal clock signal generating circuit has a function of adjusting the timing of a generated internal clock signal on the basis of a control signal in accordance with the position on the bus lines of a memory module having this internal clock signal generating circuit.
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