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Abstract

A synchronous quad clock domain system synchronizes an external primary and secondary clock (130, 132) with an internal primary and secondary clock (134, 136). The rising edge of the internal primary and secondary clock signals are matched and a synchronous multiple ratio is applied to the internal primary clock signal to produce the internal secondary clock signal. The phase of the internal and external secondary clock signals are matched. The external secondary clock signal is sampled to produce a external sample signature and the external sample signature is matched to a pattern corresponding to the synchronous multiple ratio to produce an external clock cycle signal. The internal secondary clock signal is also sampled to produce an internal clock cycle signal. The internal and external clock cycle signals are compared and a phase adjust signal is provided to match the phase of the internal and external secondary clock signals.

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First Claim