Low profile package for plural semiconductor dies
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Sep 17, 2002
Grant Date -
N/A
app pub date -
Jun 30, 2000
filing date -
Jun 30, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A package for one or more semiconductor die is disclosed, along with a method of making the package. In one embodiment, the package includes a substrate having opposed top and bottom surfaces and an aperture therebetween. The substrate includes an insulative layer and top and bottom metal layers on the insulative layer around the aperture. The metal layers are electrically connected through the insulative layer. At least one die is supported within the aperture by an insulative encapsulant material. The bottom surface of the die is exposed. In alternative embodiments, a stack including a plurality of die (e.g., two die) are supported in the aperture. Rectangular metal are provided in a single row on the bottom surface of the substrate along at least two edges of the package.
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