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Abstract

A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes a same-gate symmetrical design and reverse polarity control signals to overcome disadvantages of prior circuits while accommodating increasing circuit speeds. The circuit employs all NAND gates on the select lines controlling multiplexer transmission gates rather than NAND gates and a NOR gate. The design may also be implemented using AND gates. In addition to using a NAND gate where prior designs use a NOR gate, the polarity of the flip-flop output which drives the additional NAND gate is inverted, and the polarity of the input to the transmission gate driven by the additional NAND gate is also inverted. The circuit thus provides a symmetric design using the same NAND logic gates on all select lines while preserving functionality of the n-to-1 multiplexer. The symmetry of the design avoids problems which are inherent to prior asymmetrical designs is having NAND gates and a NOR gate, such as uneven delays on the select lines which can result in a short circuit for brief periods of time and the additional design effort required to overcome loading on NOR gate inputs resulting from NOR gates having increased area.

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First Claim