Method for extraction of inductances in integrated circuits
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United States of America Patent
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Sep 17, 2002
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app pub date -
Feb 2, 2000
filing date -
Feb 2, 1999
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Abstract
Disclosed is an approximate inductance extraction method that can be practically applied to full-chip inductance extraction of complex integrated circuits. The method results in a positive semi-definite inductance matrix and achieves sparsity of the inductance matrix by breaking inductive couplings between power-ground lines and signal lines and by using a set of geometry based decomposition rules to eliminate insignificant coupling interactions between signal lines. By taking advantage of the ever-present availability of power-ground lines as high frequency current returns while preserving inductive coupling between signal lines, the disclosed method has demonstrated higher efficiency and accuracy than other inductance matrix sparsification techniques.
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