Test, reset and communications operations in an ARC fault circuit interrupter with optional memory and/or backup power
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United States of America Patent
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Sep 24, 2002
Issued Date -
N/A
app pub date -
Dec 17, 1999
filing date -
Feb 19, 1998
priority date (Note) -
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Abstract
An arc fault circuit interrupter system for use with an electrical circuit includes an arcing fault detector which monitors the electrical circuit and a controller which generates a trip signal in response to the detection of arcing faults. The controller may also generate one or more communication signals corresponding to information relating to the operation of the arcing fault circuit interrupter. The system may also include one or more of the following: a communication port which communicates to a user the information relating to operation of the arc fault circuit interrupter in response to the communication signals; a memory for retaining predetermined information related to the condition and operation of the arcing fault circuit interrupter, with or without a backup memory; and a combined self-test/reset switch.
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