High speed programmable address decoder
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United States of America Patent
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Oct 1, 2002
Issued Date -
N/A
app pub date -
Apr 9, 2001
filing date -
Jan 29, 1999
priority date (Note) -
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Abstract
A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to allow addressing of the memory in different data widths and depths. The circuitry can be used as column address decoder or row address decoder, or both. In a dual-port memory implementation of the memory, there can be two instances of each of the decoders, one for writing and one for reading.
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