Split-bank architecture for high performance SDRAMs
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United States of America Patent
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Oct 1, 2002
Grant Date -
N/A
app pub date -
Feb 6, 2001
filing date -
Feb 8, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the memory bank segments are proximally positioned relative to associated I/Os. In this way, the delay times from each of the memory bank segments to their respective I/Os are substantially equal to each other. In addition, the proximal positioning of the memory banks results in reduced signal delays due to reduced signal paths from each bank segment and respective I/O.
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