Semiconductor memory device having data masking pin and memory system including the same
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United States of America Patent
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Oct 1, 2002
Grant Date -
Mar 21, 2002
app pub date -
Jun 21, 2001
filing date -
Sep 16, 2000
priority date (Note) -
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Abstract
A synchronous DRAM which can mix memory modules having different organizations in a memory system and a memory system including the same are provided. The synchronous DRAM includes a data masking pin which receives a data masking signal for masking input data during writing, and outputs the same signal as a data strobe signal through the data masking pin during reading. The synchronous DRAM further includes a data masking signal input buffer for buffering the data masking signal received from the data masking pin and outputting it to an internal circuit, and an auxiliary data strobe signal output buffer for buffering an internal data strobe signal generated internally and outputting it to the data masking pin. Also, the synchronous DRAM further includes a mode register which can be controlled externally, and the auxiliary data strobe signal output buffer is controlled by an output signal of the mode register.
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