Method and system for wafer level testing and burning-in semiconductor components

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United States of America Patent

PATENT NO 6462575
SERIAL NO

09650342

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Abstract

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A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of providing all of the components on the wafer with resilient contact structures, such as metal pins having integral spring segments. The resilient contact structures are used to test the components to identify functional and non-functional components. Following this test, the resilient contact structures on the non-functional components are deformed, such that electrical communication with the non-functional components is prevented in a subsequent burn-in test. This permits the burn-in test to be performed using 'shared resources' test equipment. A deformation apparatus for deforming the resilient contact structures includes a deformation block configured to compress, bend or shape the resilient contact structures on the non-functional dice. A test system for performing the burn-in test includes the deformation apparatus, a burn-in board for retaining multiple substrates, a test board having test pads for electrically engaging the resilient contact structures on the functional components, and a test circuitry in electrical communication with the test board. An alternate embodiment test system includes a deformation apparatus configured to electrically engage the resilient contact structures, and to apply test signals to the components to identify defective components.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC A CORP OF DELAWARE2805 E COLUMBIA ROAD BOISE ID 83706

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cram, Daniel P Boise, ID 51 546

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