Configurable memory structures in a programmable logic device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 8, 2002
Grant Date -
N/A
app pub date -
Jan 16, 2001
filing date -
Apr 28, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully