System and method for adjusting a sampling time in a logic analyzer
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United States of America Patent
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Oct 8, 2002
Grant Date -
N/A
app pub date -
Aug 16, 1999
filing date -
Aug 16, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system and method are provided for detecting a stable region in a data signal to facilitate the alignment between a data signal and a corresponding clock signal. The system includes a processor coupled to a local interface and a memory coupled to the local interface. The system also includes a boundary detection circuit configured to perform a simultaneous sampling of a reference signal and a delayed reference signal to ascertain a degree of stability of a position in the reference signal. The reference signal is the signal received from the target system and the delayed reference signal is a delayed copy of the reference signal. The system also includes boundary detection logic stored on the memory and executed by the processor to control the operation of the boundary detection circuit. The boundary detection logic includes logic to detect a boundary of the stable region of the reference.
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