Low latency input-output interface
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 8, 2002
Grant Date -
N/A
app pub date -
Jan 19, 2000
filing date -
Jan 19, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.
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