Spawn-join instruction set architecture for providing explicit multithreading
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United States of America Patent
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Oct 8, 2002
Grant Date -
N/A
app pub date -
Sep 7, 1999
filing date -
Mar 21, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (30), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.
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