Cell-layout method in integrated circuit devices

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United States of America Patent

PATENT NO 6463575
SERIAL NO

09493606

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Abstract

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A cell-layout method comprises the steps of: establishing cut lines in vertical and horizontal directions for substrate division; assuming an entire substrate as one cell-layout region and assigning all cells of an integrated circuit to the region; defining a set of the cells within the cell-layout region; determining a direction of the cut line to division-process the cell-layout region; selecting one cut line per row or column of non-processed cut lines in the horizontal or vertical direction based on the determined direction; determining a cell in the cell-layout region by implementing a Min-Cut division in cluster unit to the selected cut line, and implementing the division in parallel for a plurality of cut lines, thereby determining cells to be placed on the cell-layout region, with the result of cutting a process time in a large scale integrated circuit and avoiding local wire congestion.

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Patent Owner(s)

  • MITSUBISHI DENKI KABUSHIKI KAISHA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Takahashi, Kazuhiro Tokyo, JP 419 3644

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