Implementing wide multiplexers in an FPGA using a horizontal chain structure
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United States of America Patent
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Oct 15, 2002
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app pub date -
May 15, 2001
filing date -
May 15, 2001
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Abstract
Methods and structures for implementing wide multiplexers in programmable logic devices (PLDs) in a distributed fashion. According to one embodiment, a configurable logic structure includes a function generator, a carry multiplexer, and an OR gate. The function generator is configured to implement a multiplexing function (under control of a first select signal) and an AND function (ANDing the output of the multiplexer with a second select signal). The carry multiplexer is configured to perform an AND function between an output of the function generator and a third select signal. Thus, with three select signals available, an 8-to-1 multiplexer can be implemented by combining the outputs of four different logic structures that use different values of the select signals. This combination of outputs is performed by forming an OR chain, with the OR input of each stage being provided by the associated carry multiplexer.
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