Reduced static phase error CMOS PLL charge pump
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United States of America Patent
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Oct 15, 2002
Grant Date -
N/A
app pub date -
May 4, 2001
filing date -
May 4, 2001
priority date (Note) -
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Importance
Abstract
An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.
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