Laterally situated stress/strain relieving lead for a semiconductor chip package

United States of America Patent

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Oct 22, 2002
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Apr 12, 2000
filing date
Sep 8, 1995

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Abstract

A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.

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TESSERA INC	3025 ORCHARD PARKWAY SAN JOSE CA 95134

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H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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Inventor Name	Address	# of filed Patents	Total Citations
Distefano, Thomas H	Monte Sereno, CA	191	14662
Fjelstad, Joseph	Sunnyvale, CA	130	7144
Smith, John W	Palo Alto, CA	213	9165

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Laterally situated stress/strain relieving lead for a semiconductor chip package

Number of patents in Portfolio can not be more than 2000

United States of America Patent

09547200

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PATENT NO	6468836
SERIAL NO	09547200
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09547200

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