Queue system involving SRAM head, SRAM tail and DRAM body
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United States of America Patent
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Oct 22, 2002
Grant Date -
N/A
app pub date -
Oct 13, 1999
filing date -
Oct 13, 1999
priority date (Note) -
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Abstract
A device for queuing information combines the speed of SRAM with the low cost and low power consumption of DRAM, affording substantial expansion of high-speed data storage in queues without corresponding increases in costs. The queues have a variable size, and provide fast, flexible and efficient data storage via an SRAM interface and a DRAM body. The queues may hold pointers to buffer addresses or other data that allow manipulation of information in the buffers via manipulation of the queues. Particular utility for this mechanism exists in situations for which high-speed access to queues is beneficial, flexible queue size is advantageous, and/or the smaller size and lower cost of DRAM compared to SRAM is of value.
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