Sequential memory access cache controller
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Oct 22, 2002
Grant Date -
N/A
app pub date -
Jun 26, 2000
filing date -
Nov 13, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A cache controller is disclosed that includes a first means for determining when data specified by a memory address requested by the processor is absent from the cache, and a second means for determining when the processor reads sequential memory addresses. The second means is activated when the first means detects that data is absent from the cache and causes the cache controller to (i) permit data to be supplied from the main memory to the processor, even when the data is available in the cache; (ii) inhibit the first means from determining whether requested data is available in the cache; and (iii) update the cache with data supplied to the processor from the main memory.
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