System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops
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United States of America Patent
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Oct 22, 2002
Grant Date -
N/A
app pub date -
Dec 29, 2000
filing date -
Dec 29, 2000
priority date (Note) -
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Abstract
An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.
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