Method for manufacturing an interconnect structure for stacked semiconductor device

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United States of America Patent

PATENT NO 6472293
SERIAL NO

09997878

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

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Patent Owner(s)

  • FUJITSU SEMICONDUCTOR LIMITED;LAPIS SEMICONDUCTOR CO., LTD.;MATSUSHITA ELECTRONICS CORPORATION;NEC CORPORATION;RENESAS ELECTRONICS CORPORATION;ROHM CO., LTD.;SANYO ELECTRIC CO., LTD.;SHARP KABUSHIKI KAISHA;SONY CORPORATION;KABUSHIKI KAISHA TOSHIBA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Suga, Tadatomo Tokyo, JP 50 1426

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