Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 5, 2002
Grant Date -
N/A
app pub date -
Feb 26, 2001
filing date -
Feb 26, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully