Method for producing trenches for DRAM cell configurations
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United States of America Patent
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Nov 5, 2002
Grant Date -
Oct 25, 2001
app pub date -
Jan 3, 2001
filing date -
Jan 3, 2000
priority date (Note) -
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Abstract
The invention relates to a method for producing trenches for manufacturing storage capacitors in DRAM cell configurations. In the method, a two-stage hard mask having a first mask layer (1) and an underlying second mask layer (2) is used. A resist mask is applied to the mask layers (1, 2). The trenches are structured by etching processes, in which, in a first etching process, the first mask layer (1) is etched selectively with respect to the resist mask, and in a second etching process, the second mask layer (2) is etched selectively with respect to the first mask layer (1).
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