Semiconductor interconnection structure and method
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United States of America Patent
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Nov 5, 2002
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N/A
app pub date -
Sep 6, 2000
filing date -
May 4, 1998
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Abstract
A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material.
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