Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver
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United States of America Patent
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-
Nov 5, 2002
Grant Date -
Jul 25, 2002
app pub date -
Mar 25, 2002
filing date -
Oct 25, 1999
priority date (Note) -
Expired
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Abstract
Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
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