Sampling control loop for a receiver for digitally transmitted signals
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United States of America Patent
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Nov 5, 2002
Grant Date -
N/A
app pub date -
Sep 25, 1998
filing date -
Sep 26, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
To optimize the sampling of individual symbols (S0 to S3), a sampling control loop (1) for a circuit (2) for receiving digitally transmitted signals (s) is connected to a timing error detector (3) which determines the respective timing error values (td). To improve the control action of the sampling control loop (1), an evaluating device (11) determines a reliability value (v) from signals (I, Q; Is, Qs; sb, sp; sr) of the receiving circuit (2) and controls the sampling control loop (1) in accordance with the reliability value (v).
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