High-speed cycle clock-synchronous memory device
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United States of America Patent
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-
Nov 12, 2002
Grant Date -
Oct 11, 2001
app pub date -
Jun 5, 2001
filing date -
Jul 17, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S.gtoreq.N.gtoreq.F.
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