High speed network switch bus clock
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United States of America Patent
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Nov 12, 2002
Grant Date -
N/A
app pub date -
Jul 1, 1998
filing date -
Jul 1, 1998
priority date (Note) -
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Abstract
A high-speed network switch includes a data bus for transmitting data between devices. The data bus includes a plurality of data lines and a clock line. As packet data is received by the high-speed network switch, the packet data is divided into byte-wide cells for transmission over the data lines. While the cells are transmitted over the data lines, a half-speed clock is transmitted over the clock line. Transitions in the half-speed clock occur during transmission of the cell data. The transitions are used by a receiving device to sample the byte-wide cells.
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