Reducing internal bus speed in a bus system without reducing readout rate
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United States of America Patent
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Nov 12, 2002
Grant Date -
N/A
app pub date -
Jul 21, 1999
filing date -
Jul 22, 1998
priority date (Note) -
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Abstract
An improved bus system having input ports and output ports for transporting data is described. The bus system includes bus lines, switching elements, and a sequencing element. The bus lines channel data from the input ports to the output ports. The switching elements are configured to place data from the input ports onto the bus lines. Each of the switching elements enable one of a group of data to be placed on each of the bus lines simultaneously. The sequencing element selects a predetermined number of the group of data on the bus lines and sequentially directs the selected number of data to the output ports at different points in time.
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