Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
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United States of America Patent
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Nov 12, 2002
Grant Date -
N/A
app pub date -
Mar 1, 1999
filing date -
Mar 1, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the circuitry performs a first comparison of the values of two locations having corresponding addresses in different DUTs after reading from the locations, and in response generates the error values indicative of the first comparison. The circuitry may further perform a second comparison of the values of two different locations in the same DUT to generate further error values indicative of the second comparison.
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