IC substrate noise modeling including extracted capacitance for improved accuracy

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United States of America Patent

PATENT NO 6480986
SERIAL NO

09536256

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Abstract

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A method for extracting the capacitance value associated with a PN junction along the well-substrate interface for use in modeling the substrate. The method includes receiving the 2-D or 1-D mesh doping profile. The method includes finding a junction curve or transition region that represents the transition between the well and the substrate bulk. The method further includes finding a set of parameters .alpha.,.beta. and .gamma. to characterize the junction at a point or a vertical discretization along the transition. During modeling, the set of parameters .alpha., .beta. and .gamma. is then employed, along with the input bias voltage value, to calculate the thickness of the depletion region, which is in turn employed to calculate the capacitance for the well-substrate junction. The capacitance calculated is then employed to more accurately model the junction, which leads to a more accurate model for the substrate.

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Patent Owner(s)

Patent OwnerAddress
SIMPLEX SOLUTIONS INC521 ALMANOR AVENUE SUNNYVALE CA 94086

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Richer, Jean-Michel Voiron, FR 5 36

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