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Abstract

A memory device is provided that latches a plurality of data larger than a number of input or output bits and sequentially controls the transmission of the data for input/output preferably using a higher speed clock. The memory device can be a synchronous SRAM circuit that includes a control unit outputting a burst mode signal, an address decoder receiving an externally inputted address signal and the burst mode signal, outputting an internal address signal and a block coding signal, and a counter enabled by the burst mode signal and counting the block coding signal and outputting a coding signal. A multiplexer receives cell data from a plurality of sense amplifiers of the sense amplifier to concurrently latch the plurality of cell data having a prescribed number of bits larger than the number of external input and output bits and outputs one cell data among a plurality of the cell data in accordance with the coding signal. The latched data can be sequentially output to the outside using the counter.

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First Claim