Importance

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Abstract

A packetized dynamic random access memory ('DRAM') receives command packets each of which contain a plurality of packet words. The packet words in each command packet are combined to produce a command word. A portion of a command word for each command packet is stored in one of a plurality of command units so that a plurality of packet words may be stored in respective command units at the same time. The command units then generate respective command signals corresponding to the stored command word, with command signals being generated by only one command unit at a time. A control circuit prevents each command word from being stored in more than one command unit, and prevents a command word from overwriting a command word stored in a command unit before command signals have been generated from the stored command word. The control circuit arranges the command units in a hierarchy, and enables a command unit to store a command word only if the command unit is not busy and all of the command units having a higher hierarchy are busy.

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First Claim