Method of generating integrated circuit feature layout for improved chemical mechanical polishing
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United States of America Patent
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Nov 26, 2002
Grant Date -
Aug 8, 2002
app pub date -
Feb 2, 2001
filing date -
Feb 2, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.
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