Electronic module having a three dimensional array of carrier-mounted integrated circuit packages
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United States of America Patent
Stats
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Nov 26, 2002
Grant Date -
Sep 26, 2002
app pub date -
Mar 13, 2000
filing date -
Mar 13, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the main circuit board. A third primary embodiment of the invention incorporates features of both the first and second primary embodiments. One of the packages is mounted on a planar surface of the carrier rightside up, while the other package is mounted on the carrier in a recess upside down. Several variants of this embodiment are possible. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the main circuit board. In the former case, the adjacent package of the package unit fits within a recess on the main circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the main circuit board. For any of the three primary main embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the main circuit board or connection may be made directly between the leads of one package and the interconnection pads of the circuit board.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| LEGACY ELECTRONICS INC | 300 NORTH DAKOTA AVENUE SUITE 314 SIOUX FALLS SD 57104 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Engle, Jason C | San Clemente, CA | 10 | 303 |
| Kledzik, Kenneth J | San Clemente, CA | 17 | 713 |
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Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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